Endicott Interconnect Technologies CoreEZT Thin Core FC Technology

Thin Core Flip Chip Package Provides 199 Micron Via-to-Via Core Pitch
Endicott, NY - April 2007

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199 micron core via pitch, 50 micron laser drilled vias

25 micron LW/LS, migrating to 20 micron in ‘062X the board level reliability of a standard FC PBGA or FC ceramic BGA

Full signal wiring on both sides of core

Thin core (200 micron) reduces inductance

RoHS compliant

6, 8, 10 and 12 layersUp to 4 full strip line signal layers

Low cost material set

Thin core build-upHigh speed differential pair designs

Parts available in any shape, enabling the merger of dense circuitization found in chip packaging with conﬁguration variety found in traditional PCB technology

EI’s CoreEZ™ semiconductor package utilizes the HyperBGA^® manufacturing platform to offer a thin core build-up ﬂip chip package with very dense core vias using a cost sensitive material set. The core via density provides 199 micron via-to-via core pitch resulting in an essentially coreless structure. High core via density is achieved using smaller pads and the same 50 micron laser drilled holes used in producing HyperBGA^® to unblock wiring channels through the core. This enables CoreEZ™ to provide up to 2 times the number of signal layers as a standard build-up package that uses mechanically drilled core vias with large capture pads. The end result is an extremely cost effective solution that allows full strip line signal layers on both sides of the core.

Component cost is further reduced by enabling die shrink through die pad pitch reduction down to 150 microns. In addition, the thinness of the core provides improved power distribution and the ability to dissipate chip thermal power into the PCB.

Applications

CoreEZ™ is an excellent choice for applications requiring low cost build-up materials along with high reliability, performance and wireability. It is also nicely suited to aerospace applications requiring radiation tolerance.

CoreEZ Datasheet

CoreEZ Specification Chart

Technical Papers

“Simulation and Measurement of High Speed Serial Link Performance in Dense, Thin Core Flip Chip Package” presented at Electronic Components and Technology Conference (ECTC) 2006. click here

“Flip Chip Assembly Challenges Using High Density, Thin Core Carriers” presented at Electronic Components and Technology Conference (ECTC) 2005. click here

“Thermal Performance of a Thin High Interconnect Density Organic Substrate for Flip Chip Applications” presented at Electronic Components and Technology Conference (ECTC) 2005. click here

| HyperBGA | CoreEZ™ | Wire Bond PBGA |